The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIGS. 1, 2A and 2B, non-volatile semiconductor memory 10 may include flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM, multi-state memory, etc. The non-volatile semiconductor memory 10 may include one or more arrays 16. The array 16 may be arranged as B memory blocks 18-1, 18-2, . . . , and 18-B (collectively referred to as blocks 18).
In FIG. 2A, each block 18 includes P pages 20-1, 20-2, . . . , and 20-P (collectively referred to as pages 20). In FIG. 2B, each page 20 may include a plurality of memory cells that are associated with a data portion 24 and may include other memory cells that are associated with an overhead data portion 26 such as error checking and correcting (ECC) data or other (O) overhead data.
The non-volatile semiconductor memory 10 typically communicates with a memory control module of a host device. Usually, the control module addresses the memory using a hardwired block size. Pages in the block may also have a hardwired physical page size and may therefore be referred to as physical pages. The number of memory cells in the data and overhead portions 24 and 26, respectively, may also be hardwired.
For example only, a NAND flash array may include 16384 blocks for a total of 2 Gigabytes (GB) of memory. Each block may include 128 kilobytes (kB) in 64 pages. Each page may include 2112 bytes. Of the 2112 bytes, 2048 bytes may be associated with the data portion and 64 bytes may be associated with the overhead portion. Each memory cell may store a bit. To erase data stored in the array, the memory control module typically requires either an entire block and/or an entire page to be erased.
In FIG. 2C, the memory block 18 includes physical pages 50-1, 50-2, . . . , and 50-P (collectively referred to as pages 50). Each page 50 includes Y memory cells (memory cells 46-1, 46-2, . . . , and 46-Y) for the data portion and Z memory cells (memory cells 46-(Y+1), 46(Y+2), . . . , and 46(Y+Z)) for the overhead portion, where Y and Z are fixed values for a particular memory control module. During a first write operation for a first write data block, the memory control module writes data to pages 50-1 and 50-2 and part of page 50-3. During a second write operation for a second write data block, data is written to pages 50-4 and 50-5 and part of page 50-6. The remaining memory cells in pages 50-3 and 50-6 are unused.
Referring now to FIG. 2D, another memory block 80 is illustrated that includes both physical and logical pages. A memory control module (not shown) may format physical pages 50-1 to 50-6 to appear as logical pages 51-1 to 51-3 for read/write operations. In other words, data is written to memory blocks according to the logical pages instead of according to the physical pages.